The present invention relates to a data processing system, a microcontroller, and a semiconductor device, in particular, relates to technology which is effective when applied to the data processing system requiring low power consumption.
A data processing system, such as a mobile terminal and a server, is configured by mutually coupling plural electronic parts, such as a microcontroller, a memory, a sensor, and a power IC, in order to realize a desired function. In recent years, there is an increasing demand of power saving of a data processing system. In order to realize the power saving of a data processing system, it is indispensable to suppress the power consumption of each device (for example, a semiconductor integrated circuit) which configures the data processing system.
As the power saving technology of a semiconductor integrated circuit, the technique called power gating has been attracting attention in recent years. In the technique called power gating, power supply to a non-operating circuit block of a semiconductor integrated circuit is cut off, thereby suppressing a leakage current of the circuit block concerned and reducing the power consumption of the entire semiconductor integrated circuit.
In recent years, the concept of this power gating is applied to a data processing system, and consideration is given to attaining the power saving of the entire data processing system by controlling separately the supply and cutoff of power to each device implemented in a mounting board. For example, Patent Literature 1 discloses technology of performing the power supply and power cutoff to each memory chip in a memory module provided with plural memory chips. Specifically, Patent Literature 1 discloses the technique of shifting the timing of the power supply and the power cutoff to plural memory chips with the use of a power-on control signal to instruct the power supply and the power cutoff.
However, when an SRAM and a DRAM are employed as an external memory of a microcontroller in the data processing system, it is often difficult to perform the power cutoff because these external memories are volatile. Accordingly, for attaining the further power saving, in recent years, consideration is given to the employment of a nonvolatile RAM (NVRAM), such as an MRAM and an FRAM (a registered trademark, the same in the following), in which data is not lost even if the power is cut off. By employing an NVRAM in lieu of an SRAM or a DRAM, it becomes possible to perform power cutoff of the external memory easily, therefore, the further power saving of the system can be expected.
(Patent Literature 1)
Published Japanese Unexamined Patent Application No. 2007-164822